Samsung Considers Chip Packaging Test Line In Japan As It Seeks Deeper Cooperation Sources
© Thomson Reuters PHOTO: Samsung is considering building a state-of-the-art chip packaging test line in Japan - sourceMaki Shiraky and Joyce Lee
TOKYO/SEOUL (Reuters) - South Korea's Samsung Electronics Co Ltd is considering setting up a test track in Japan for chip packages. The five said they would develop their advanced package business and forge closer ties with Japanese hardware and semiconductor makers.
© Thomson Reuters PHOTO: The Samsung Electronics logo is seen at its headquarters in Seoul.This will be the first test track in Japan for Samsung, the world's largest manufacturer of memory chips.
It also comes as the United States increasingly calls on allies to work together against China's growing power in advanced chips and technology.
Japan said on Friday it would limit exports of 23 types of chip-making tools, aligning technology trade controls with moves by the United States to limit China's ability to make advanced chips.
Samsung wants to locate the facility in Kanagawa Prefecture, near Tokyo, where it already has a research and development center, said the four people, who declined to be named because the information was not publicly available.
While details have yet to be agreed, including timing, the investment is likely to total tens of billions of yen ($75 million), one of the sources said.
According to two sources, Samsung wants to deepen cooperation with Japanese companies. Japan is attractive because of relatively low labor costs and the presence of leading chip equipment and materials manufacturers, giving Samsung access to the local "ecosystem," one said.
However, one of the sources said discussions are still at an early stage, adding that the South Korean company is considering several options and nothing has been decided yet.
Samsung declined to comment.
The company wanted to develop an advanced packaging method that involves placing chips with different functions in a single package to increase overall capabilities and limit the added cost of more complex chips.
This 3D packaging can also help manufacturers improve chip performance even as they push the physical limits of small chip functionality.
The test line will cover the so-called internal chip manufacturing process, which refers to the process by which semiconductors are cut and assembled into products, the five people said.
South Korean President Yoon Seok-yeol this month made the first visit of a South Korean leader to Japan in 12 years, where he met with business leaders of the two countries.
The leaders of the two US allies have pledged to work more closely together on chips and technology. Washington is working to boost trade diplomacy with the two countries, focusing on chips to counter China.
Taiwan Semiconductor Manufacturing Co Ltd (TSMC), the world's largest contract chipmaker, last year opened a research center in the Japanese city of Tsukuba, northeast of Tokyo, at a cost of about ¥37 billion, of which ¥19 billion came from Japan. . the government will come. .
TSMC facilities include a research production line.
Last year, Samsung set up a state-of-the-art packaging team in South Korea. On Thursday, the country finalized a bill that would offer semiconductor companies and other domestic investors huge tax breaks. Samsung said this month it plans to invest $230 billion over 20 years in South Korea's chip industry.
(1 dollar = 132.5200 yen)
(Reporting by Maki Shiraki and Joyce Lee; Editing by David Dolan and Mien Kim)
